Nonvolatile memory device using a varistor as a current limiter element

ABSTRACT

Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. The electrical properties of the current limiting component are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element of the nonvolatile memory device. In some embodiments, the current limiting component comprises a varistor that is a current limiting material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/399,815, filed Feb. 17, 2012, now U.S. Pat. No. 8,686,386, which isincorporated by reference herein in its entirety for all purposes.

BACKGROUND

This invention relates to nonvolatile memory elements, and moreparticularly, to methods for forming resistive switching memory elementsused in nonvolatile memory devices.

Nonvolatile memory elements are used in systems in which persistentstorage is required. For example, digital cameras use nonvolatile memorycards to store images and digital music players use nonvolatile memoryto store audio data. Nonvolatile memory is also used to persistentlystore data in computer environments.

Nonvolatile memory is often formed using electrically-erasableprogrammable read only memory (EEPROM) technology. This type ofnonvolatile memory contains floating gate transistors that can beselectively programmed or erased by application of suitable voltages totheir terminals.

As fabrication techniques improve, it is becoming possible to fabricatenonvolatile memory elements with increasingly smaller dimensions.However, as device dimensions shrink, scaling issues are posingchallenges for traditional nonvolatile memory technology. This has ledto the investigation of alternative nonvolatile memory technologies,including resistive switching nonvolatile memory.

Resistive switching nonvolatile memory is formed using memory elementsthat have two or more stable states with different resistances. Bistablememory has two stable states. A bistable memory element can be placed ina high resistance state or a low resistance state by application ofsuitable voltages or currents. Voltage pulses are typically used toswitch the memory element from one resistance state to the other.Nondestructive read operations can be performed to ascertain the valueof a data bit that is stored in a memory cell.

Resistive switching based on transition metal oxide switching elementsformed of metal oxide (MO) films has been demonstrated. Although metaloxide (MO) films such as these exhibit bistability, the resistance ofthese films and/or the ratio of the high-to-low resistance states is(are) often insufficient to be of use within a practical nonvolatilememory device. For instance, the resistance states of the metal oxidefilm should preferably be significant as compared to that of the system(e.g., the memory device and associated circuitry) so that any change inthe resistance state change is perceptible.

Because the variation in the difference in the resistive states isrelated to the resistance of the resistive switching layer, it is oftenhard to use a low resistance metal oxide film to form a reliablenonvolatile memory device. For example, in a nonvolatile memory that hasconductive lines formed of a relatively high resistance metal such astungsten, the resistance of the conductive lines may overwhelm theresistance of the metal oxide resistive switching element if itsresistance was not sufficiently high. This may make it difficult orimpossible to sense the state of the bistable metal oxide resistiveswitching element.

Similar issues can arise from integration of the resistive switchingmemory element with current steering elements, such as diodes and/orresistors. The resistance of the resistive switching memory element (atleast in its high resistance state) is preferably significant comparedto the resistance of the current steering elements, so that theunvarying resistance of the current steering element does not dominatethe resistance of the switching memory element, and thus reduce themeasurable difference between the “on” and “off” states of the formedmemory device (i.e., logic states of the device).

However, because the power that can be delivered to a circuit containinga series of resistive switching memory elements and current steeringelements is typically limited in most conventional nonvolatile memorydevices (e.g., CMOS driven devices), it is desirable to form each of theresistive switching memory elements and current steering elements in thecircuit so that the voltage drop across each of these elements is small,and thus resistance of the series connected elements does not cause thecurrent to decrease to an undesirable level due to the fixed appliedvoltage (e.g., ˜2-5 volts).

As nonvolatile memory device sizes shrink, it is important to reduce therequired currents and voltages that are necessary to reliably set, resetand/or determine the desired “on” and “off” states of the device tominimize overall power consumption of the memory chip as well asresistive heating of the device and cross-talk between adjacent devices.

Moreover, as nonvolatile memory device sizes shrink it becomesincreasingly necessary to assure that the “set” and “reset” currentsused to change the state of the memory element are not too large torequire higher voltage transistors for chip control circuitry, as wellas to minimize damage to or alter the electrical or physical propertiesof the one or more layers found in the formed memory device. A largecurrent flowing through the current carrying lines in a memory arrayalso can undesirably alter or disturb the memory state of otherinterconnected devices or possibly damage portions of adjacent connecteddevices, due to an appreciable amount of “cross-talk” created betweenthem.

There is a need to limit and/or minimize the required current used tosense and program the logic states of each of the interconnected devicesto reduce chip overall power consumption and improve device longevityand reduce the possibility of cross-talk between adjacently connecteddevices, which can alter a nonvolatile memory's device state. It is alsodesirable to form a nonvolatile memory device that has low programmingcurrents when switching the device between the “on” and “off” states.

Certain materials are known and have been used within the device tolimit the current across the nonvolatile memory device while trying toresolve the cross-talk issue and lower the programming currents, butthese materials through fabrication of the device or through regulardevice operation can contaminate or alter the properties of the metaloxide switching films and affect the performance of the switching memoryelement. Therefore, it is desirable to form a nonvolatile memory devicethat requires low programming currents to change the device between the“on” and “off” states.

SUMMARY

Embodiments of the invention generally relate to a resistive switchingnonvolatile memory device having a passive current limiter layer and abarrier layer structure disposed between at least one of the electrodesand a variable resistance layer formed in the nonvolatile memory device.The resistive switching memory elements may be formed as part of ahigh-capacity nonvolatile memory integrated circuit, which can be usedin various electronic devices, such as digital cameras, mobiletelephones, handheld computers, and music players.

The resistive switching nonvolatile memory device comprises a variableresistance layer and current limiter layer that are configured to adjustthe nonvolatile memory device's performance, such as lowering the formeddevice's switching currents and reducing the device's forming voltage,and reducing the performance variation from one formed device toanother.

The present invention may provide a nonvolatile memory element,comprising a variable resistance layer comprising a metal oxide disposedbetween a first electrode layer and a second electrode layer with aseparation layer comprising an oxygen deficient material disposed abovethe variable resistance layer and also a current limiter layer disposedbetween the first electrode layer and the separation layer.

Embodiments of the present invention may further provide a nonvolatilememory element including a variable resistance layer disposed between afirst electrode layer and a second electrode layer with the variableresistance comprising a metal oxide. A current limiter layer comprisinga varistor is disposed between the first electrode layer and thevariable resistance layer, and a separation layer operable to inhibitthe flow of oxygen ions is disposed between the current limiter layerand the variable resistance layer. The nonvolatile memory elementincludes a first stabilizing layer and a second stabilizing layerdisposed on either side of the current limiter layer with thestabilizing layers operable to provide oxygen to the current limiterlayer.

Embodiments of the present invention may further provide a method offorming the nonvolatile memory elements described above.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Theappended drawings illustrate only typical embodiments of this inventionand are therefore not to be considered limiting of its scope, for theinvention may admit to other equally effective embodiments.

FIG. 1 illustrates an array of resistive switching memory elements inaccordance with an embodiment of the invention.

FIG. 2A is schematic representation of a memory device in accordancewith an embodiment of the invention.

FIG. 2B is schematic representation of a memory device having a diodetype current steering element in accordance with an embodiment of theinvention.

FIG. 2C is schematic representation of an array of memory devices inaccordance with an embodiment of the invention.

FIG. 2D is schematic representation of an array of memory devices inaccordance with an embodiment of the invention.

FIG. 3A is a schematic side cross-sectional view of a standard memoryelement disposed in a nonvolatile memory device.

FIG. 3B is a schematic representation of an electrical circuit formed inthe standard memory element illustrated in FIG. 3A.

FIG. 4A is a graph illustrating the current (I) versus voltage (V)characteristics of the high and low resistance load lines of a variableresistance layer in accordance with an embodiment of the invention.

FIG. 4B is a current versus time plot illustrating the effect ofdelivering bipolar type switching pulses through a memory element inaccordance with an embodiment of the invention.

FIG. 5A is a schematic side cross-sectional view of a memory elementdisposed in a nonvolatile memory device in accordance with an embodimentof the invention.

FIG. 5B is a schematic side cross-sectional view of a memory elementdisposed in a nonvolatile memory device in accordance with a furtherembodiment of the invention.

FIG. 5C is a schematic representation of an electrical circuit formed inthe memory element illustrated in FIG. 5A and FIG. 5B in accordance withan embodiment of the invention.

FIG. 6 is a schematic depiction of a process for forming the switchingmemory device according to some embodiments of the invention.

Although the foregoing is directed to embodiments of the presentinvention, other and further embodiments of the invention may be devisedwithout departing from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

DETAILED DESCRIPTION

Embodiments of the invention generally include a method of forming anonvolatile memory device that contains a resistive switching memoryelement that has an improved device switching performance and increasedusable lifetime, due to the addition of a current limiting componentdisposed therein. In some embodiments, the current limiting componentcomprises a varistor that is a resistive material that is disposedwithin a formed resistive switching memory element in a nonvolatileresistive switching memory device.

The electrical properties of the formed current limiting layer areconfigured to lower the current flow through the variable resistancelayer by adding a fixed series resistance in the formed nonvolatileresistive switching memory device. It is generally desirable to form thecurrent limiting layer so that its material and electrical propertieswill not degrade or breakdown during the often high current “burn-in”type device preparation steps, such as the “electrical forming” process,and also during normal repetitive operation of the nonvolatile resistiveswitching memory device.

An illustrative memory array 100 of nonvolatile resistive switchingmemory devices 200 (hereafter switching memory device 200), which eachgenerally include at least one resistive switching memory element 112,is illustrated in FIG. 1. Memory array 100 may be part of a largermemory device or other integrated circuit structure, such as a system ona chip type device. Read and write circuitry is connected to switchingmemory devices 200 using word-lines and bit-lines, which are referred toherein generally as electrodes 102 and 118, and are used to read from orwrite data into the memory element 200.

Electrodes 102 and 118, generally include one or more conductive layersthat each have a desired function in the array of switching memorydevices 200. In some configurations, the electrodes 102 and 118 eachcomprise two or more conductive layers in which a first conductive layeris used to interconnect the multiple switching memory devices 200 and asecond conductive layer is disposed in each switching memory device 200to provide a desirable electrical interface (e.g., desirable workfunction) to the adjacent components in the switching memory device 200.

Individual switching memory devices 200 or groups of switching memorydevices 200 can be accessed using appropriate sets of word-lines andbit-lines, or electrodes 102 and 118. The memory elements 112 in theswitching memory devices 200 may be formed from one or more layers 114of materials, as indicated schematically in FIG. 1. In addition, memoryarrays such as memory array 100 can be stacked in a vertical fashion tomake multilayer memory array structures. The use of resistive switchingmemory elements to form memory arrays is merely illustrative, and oneskilled in the art will appreciate that the formed devices may be usedin other device applications without deviating from the basic scope ofthe invention described herein.

FIG. 2A schematically illustrates one example of a switching memorydevice 200 that contains a memory element 112 and an optional currentsteering device 216, which are both disposed between the electrodes 102and 118. In one configuration, the current steering device 216 is anintervening electrical component, such as a p-n junction diode, p-i-ndiode, transistor, or other similar device that is disposed betweenelectrode 102 and memory element 112, or between the electrode 118 andmemory element 112. In one example, the current steering device 216 mayinclude two or more layers of semiconductor material, such as two ormore doped silicon layers, that are configured to allow or inhibit thecurrent flow in different directions through the memory element 112 whenthat memory element is not selected to read.

FIG. 2B schematically illustrates a switching memory device 200 thatcontains a memory element 112 and a diode type current steering device216 that preferentially allows current to flow through the memory device200 in a forward direction (“I⁺”). However, due to the design of thecurrent steering device 216, a reduced current can also flow in theopposing direction through the device by the application of a reversebias to the electrodes 102 and 118.

FIG. 2C schematically illustrates an array of switching memory devices200 that are connected together to form part of a high-capacitynonvolatile memory integrated circuit. Each of the individual switchingmemory devices 200 can be accessed using appropriate sets of discreteword-lines and bit-lines, which, as noted above, may comprise at least aportion of the electrodes 102 and 118. As illustrated in FIG. 2C, eachof the switching memory devices 200 contains a memory element 112 andcurrent steering device 216 (e.g., a diode type) that are connected toat least one of the electrodes 102 and at least one of the electrodes118. The electrodes 102 and/or 118 are generally biased by circuitrythat is connected at the periphery of the memory chip on which the arrayof memory devices 200 is formed.

FIG. 2D schematically illustrates another embodiment of an array ofswitching memory devices 200 that are connected together to form part ofa high-capacity nonvolatile memory integrated circuit. As shown in FIG.2D, the current steering device 216, such as a typical MOS typetransistor, is used to selectively deliver current through the memoryelement 112 by use of the appropriate set of word-lines, bit-lines andseparate source-lines 119. As illustrated in FIG. 2D, each of theswitching memory devices 200 contains a memory element 112 and currentsteering device 216 (e.g., transistor) that are connected to at leastone of the electrodes 102, at least one of the electrodes 118 and atleast one of the source lines 119.

The source-lines 119 generally comprise one or more patterned conductivelayers (e.g., metal) that are adapted to provide a desired amount ofcurrent to the memory element 112 when the transistor in the currentsteering device is turned “on.” The electrodes 102, electrodes 118 andsource-lines 119 are typically biased by circuitry that is connected atthe periphery of the memory chip on which the array of memory devices200 is formed.

During operation, such as a read operation, the state of a memoryelement 112 in the switching memory device 200 can be sensed by applyinga sensing voltage (i.e., a “read” voltage V_(READ) (FIG. 4A)), such asapplying about +0.5 volts (V), to an appropriate set of electrodes 102and 118. Depending on its history, a memory element that is addressed inthis way may be in either a high resistance state (HRS) or a lowresistance state (LRS).

The resistance of the memory element 112 therefore determines whatdigital data is being stored by the memory element 112. If the memoryelement 112 is in the high resistance state, for example, the memoryelement may be said to contain a logic “zero” (i.e., a “0” bit). If, onthe other hand, the memory element is in the low resistance state, thememory element may be said to contain a logic “one” (i.e., a “1” bit).During a write operation, the state of a memory element can be changedby application of suitable write signals to an appropriate set ofelectrodes 102 and 118.

in some embodiments, the memory element 112 uses bipolar switching whereopposite polarity set and reset voltages are used to alter theresistance of the memory element between high and low resistance states.FIG. 4A schematically illustrates a log-log plot of current (I) versusvoltage (V) of one example of high-resistant-state (HRS) andlow-resistance-state (LRS) bipolar switching curves of a resistiveswitching type of memory element, and thus illustrates typical thresholdvalues used to set and reset the contents of a memory element 112. Inone example, initially, memory element 112 may be in a high resistancestate (e.g., storing a logic “zero”).

The high resistance state of memory element 112 can be sensed by readand write circuitry 150 (FIG. 2A) using electrodes 102 and 118. Forexample, read and write circuitry may apply a read voltage V_(READ) tomemory element 112, and can sense the resulting “off” current (I_(OFF))that flows through memory element 112. When it is desired to store alogic “one” in memory element 112, memory element 112 can be placed intoits low-resistance state. This may be accomplished by using read andwrite circuitry 150 to apply a set voltage V_(SET) (e.g., −1 V to −4 V)across electrodes 102 and 118.

In one configuration, applying a negative V_(SET) voltage to memoryelement 112 causes memory element 112 to switch to its low resistancestate. It is believed that the change in the resistive state of memoryelement 112 may be due to the redistribution or filling of traps (i.e.,“trap-mediated”), or defects, in the variable resistance layer 206 (FIG.3A), when the device is reverse biased. The defects or traps, which arecommonly formed during the deposition or initial burn-in or forming ofthe variable resistance layer 206, are often created by anon-stoichiometric material composition found in the formed variableresistance layer 206. V_(SET) and V_(RESET) are generally referred to as“switching voltages” herein.

The low resistance state of the memory element 112 can be sensed usingthe read and write circuitry 150. When a read voltage V_(READ) isapplied to resistive switching memory element 112, the read and writecircuitry 150 will sense the relatively high “on” current value(I_(ON)), indicating that memory element 112 is in its low resistancestate. When it is desired to store a logic “zero” in memory element 112,the memory element can once again be placed in its high resistance stateby applying a positive reset voltage V_(RESET) (e.g., +1 V to +5 V) tomemory element 112.

When read and write circuitry applies V_(RESET) to memory element 112,memory element 112 enters its high resistance state. When the resetvoltage V_(RESET) is removed from memory element 112, memory element 112will once again be characterized by high resistance when the readvoltage V_(READ) is applied.

Voltage pulses can be used in the programming of the memory element 112.For example, a 1 microsecond (ms) to 1 nanosecond (ns) square ortrapezoidal shaped pulse can be used to switch the memory element 112.In some embodiments, it may be desirable to adjust the length of thepulse depending on the amount of time needed to switch the memoryelement 112.

In one example, the “set” and “reset” pulses are each about 10 ns inlength. Although the discussion of the memory element 112 hereinprimarily provides bipolar switching examples, some embodiments of thememory element 112 may use unipolar switching, where the set and resetvoltages have the same polarity, without deviating from the scope of theinvention described herein.

To provide a measurable difference between the logic “zero” and logic“one” states is common to form the variable resistance layer 206 andother memory element 112 components so that the I_(ON) and I_(OFF)currents have a difference of at least five times (e.g., current ratioI_(ON)/I_(OFF)≧5). In one example, the difference between the logic“zero” and logic “one” states is at least one order of magnitude (e.g.,current ratio I_(ON)/I_(OFF)≧10).

In other words, the ratio of the electrical resistances of the variableresistance layer 206 is decreased by at least 5 to 10 times whenswitching from the high to the low resistance state. For example, theelectrical resistance of the variable resistance layer 206 in the highresistance state is at least 5 to 10 times greater than the electricalresistance of the low resistance state when applying a V_(READ) readvoltage across electrodes 102 and 118 in the device.

In an effort to prepare the memory element 112 for use, it is common toapply a forming voltage (V_(FORM)) at least once across the electrodes102, 118 to “burn-in” the device. It is believed that the application ofa forming voltage, which is typically significantly greater than theV_(RESET) and V_(SET) voltages, causes the defects that are formedwithin the variable resistance layer 206 during the device fabricationprocess to move, align and/or collect within various regions of theformed layer, causing the variable resistance layer 206 to consistentlyand reliably switch between the “on” and “off” resistive statesthroughout the memory element's life.

In one configuration, the forming voltage is between about 1 and about 5times greater than the V_(RESET) or V_(SET) voltage. In one example, theforming voltage is between about 1.4 and about 2.5 times greater thanthe V_(RESET) or V_(SET) voltage. In one example, the forming voltage isbetween about 3 and about 7 volts. However, in some cases it isdesirable to form the memory element 112 so that the application of aforming voltage is not required at all to assure that the device willperform as desired throughout its life.

FIG. 3A is a schematic side cross-sectional view of a standardun-optimized switching memory device 200A, which contains a memoryelement 112 and a current steering device 216 (e.g., a diode) that isformed over a substrate 201. In this configuration, the memory element112 generally contains a top electrode 102, variable resistance layer206 and intermediate electrode 210. FIG. 3B schematically illustrates anelectrical circuit formed in the switching memory device 200A shown inFIG. 3A.

As illustrated in FIG. 3B, the electrical circuit within the standardswitching memory device 200A includes a top electrode impedance (i.e.,resistance R_(TEL)) created by the material layer(s) in the topelectrode 102, a variable resistance layer impedance (i.e., resistanceR_(VR)) created by the material layer(s) in the variable resistancelayer 206, an intermediate electrode impedance (i.e., resistanceR_(IEL)) created by the material layer(s) in the intermediate electrode210, a current steering device impedance (i.e., resistance R_(CSD))created by the material layer(s) in the current steering device 216 anda bottom electrode impedance (i.e., resistance R_(BEL)) created by thematerial layer(s) in the bottom electrode 118.

The electrodes 102, 210 and 118 are generally formed from a conductivematerial, such as a highly conductive semiconductor material (e.g.,p-type polysilicon, n-type polysilicon) and/or metal (e.g., TiN, Al, W)to minimize the circuit resistance created between interconnecteddevices in a memory array 100. The variable resistance layer 206 can bea dielectric material, such as a metal oxide material or other similarmaterial that can be switched between at least two or more stableresistive states. It is assumed that the contact resistances between thevarious layers in the switching memory device, such as the contactresistance formed between the electrode 102 and the variable resistancelayer 206, are negligible to help reduce the complexity of thediscussion of the circuit.

Although the current steering device 216 may include two or more layersof semiconductor material that are adapted to control the flow ofcurrent through the formed memory device 200A, the resistance of each ofthe components in the current steering device 216 are not individuallydiscussed herein to minimize the complexity of the discussion, and thusan overall current steering device resistance R_(CSD) is used torepresent the overall impedance of the current steering device 216.

FIG. 4A schematically illustrates a log-log plot of current (I) versusvoltage (V) of the low-resistance-state (LRS) and high-resistant-state(HRS) curves, or load lines, of a memory element 112 having these twobistable resistive states. As illustrated in FIG. 4A, by sweeping thevoltage applied to the electrodes 102 and 118 between the V_(SET) (e.g.,−3 volts) and V_(RESET) (e.g., +4 volts), while the device is in the lowresistance state, the LRS curve can be created, and by sweeping thevoltage applied to the electrodes 102 and 118 between the V_(SET) andV_(RESET), while the device is in the high resistance state, the HRScurve can be created. As noted above, depending on the physical andelectrical characteristics of a formed variable resistance layer 206, itwill switch from the HRS to the LRS during a “set” operation when aV_(SET) is applied, and the variable resistance layer 206 will switchfrom the LRS to the HRS during a “reset” operation when a V_(RESET) isapplied.

FIG. 4B is a plot of current versus time for a plurality of bipolar type“set” and “reset” switching pulses, as illustrated by pulses 401-406,that are delivered to a switching memory device in accordance with anembodiment of the invention. In one example, as shown in FIG. 4B, adevice programming step may include the delivery of a “set” switchingpulse 411, a “reset” switching pulse 413, and two “sensing” pulses 412.

To assure that the memory element 112 reliably switches from a highresistance state to a low resistance state and vice versa, one mustassure that the “set” switching pulse 411 produces a current that isgreater than a minimum “set” current I_(MSC), which is defined as theminimum current required to flow through the variable resistance layer206 to cause it to switch from a high resistance state (e.g., 2.5 MΩ) toa low resistance state (e.g., <<250 kΩ). In one example, the high andlow resistance states of the variable resistance layer 206 may be about2.5 MΩ and about 100 kΩ, respectively.

Similarly, to assure that the memory element 112 reliably switches froma low to a high resistance state the “reset” switching pulse 413 willgenerally be delivered at a current level that is greater than a minimum“reset” current I_(MRC), which is defined as the minimum currentrequired to flow through the variable resistance layer 206 to cause itto switch from a low resistance state to a high resistance state.

The minimum “set” current I_(MSC) and minimum “reset” current I_(MRC)are related to the physical and/or electrical properties of the materialin the variable resistance layer 206, and thus may be adjusted bycareful selection of the material(s) and/or physical properties (e.g.,thickness) of the variable resistance layer 206 and by performingvarious post-processing steps on the formed layer. In one example, bycontrolling the number of defects in the formed variable resistancelayer 206, such as by adjusting the stoichiometry of the material(s)found in the variable resistance layer 206 (e.g., HfO_(1.7) vs. HfO₂)during the layer formation process, the minimum switching currents canbe adjusted.

Referring to FIG. 4A, in one example, when a “set” switching pulse 411is delivered through the standard switching memory device 200A theswitching memory device will switch from the high-resistance-state (HRS)to the low-resistance-state (LRS), as shown by the arrow 421. Thecurrent flowing through the switching memory device will shift from theinitial “set” current I_(A) to the final “set” current I_(B) during the“set” operation, due to the change in resistance (R_(VR)) of thevariable resistance layer 206. Also, the initial “set” current I_(A)will typically equal the minimum “set” current I_(MSC), discussed above.

Alternately, when a “reset” switching pulse 413 is delivered through thestandard switching memory device 200A the switching memory device willswitch from the low-resistance-state (LRS) to the high-resistance-state(HRS), as shown by the arrow 422. The current flowing through theswitching memory device will shift from the initial “reset” currentI_(C) to the final “reset” current I_(D) during the “reset” operation,due to the change in resistance (R_(VR)) of the variable resistancelayer 206.

Referring to FIG. 4B, in one example, a “set” switching pulse 411, suchas switching pulse 401, is delivered through the standard switchingmemory device 200A to create a low resistance state or logic “one”state. In this case, a set voltage V_(SET) is applied across electrodes102 and 118, which creates a first “set” current I₁ to flow through thestandard switching memory device 200A, due to the impedance of theelectrical components found in the memory element 200A.

The first “set” current I₁ is equal to the applied “set” voltage V_(SET)divided by the sum of the impedances of the standard switching memorydevice 200A. Therefore, in one example, the first “set” current I₁ mayequal the following:I₁ =V _(SET)/(R _(TEL) +R _(VR) +R _(IEL) +R _(CSD) +R _(BEL)).Because the most damage to the elements contained in the standardswitching memory device 200A will generally occur when the largestcurrent is delivered through the switching memory device, the pulse 411schematically illustrated in FIG. 4B focuses on the later stages of the“set” operation, and thus the first “set” current I₁ achieved during thelater stages of the “set” switching pulse 411 will generally equal thefinal “set” current I_(B).

In general, the first “set” current I₁ will vary during the time thatthe “set” pulse 411 is applied across the electrodes 102 and 118. Thefirst “set” current I₁ may have low current region 409 that is createddue to the electrical properties of the material as it switches from theHRS to the LRS, and also have the final “set” current region asdiscussed above. Therefore, because the actual impedance of theelectrodes is generally small, due to the need to reduce the power lossin the device, and the impedance of the variable resistance layer 206 isdesirably low at the end of the “set” operation (e.g., I₁=I_(B)) toachieve a logic “one” state the impedance of the current steering devicewill dominate the circuit (e.g.,R_(CSD)>>R_(TEL)+R_(IEL)+R_(BEL)+R_(VR)) and the impedance of thecircuit in this state is approximately equal to the impedance of thecurrent steering device (i.e., R_(CSD)).

Therefore, the magnitude of the set current I₁ created by the switchingpulse 401 will equal the maximum current, or load current I_(L) (FIG.4B), which is approximately equal to the set voltage divided by theimpedance of the current steering device (i.e.,I₁=I_(L)=˜V_(SET)/R_(CSD)). The difference between the “set” currentI_(i) and the minimum I_(MSC) current is much larger than necessary tocause the device to reliably switch to the logic “one” state. However,in practice it has been found that the high currents delivered through astandard type switching memory device 200A can permanently damage thememory element components and cause cross-talk to occur betweenadjacently connected memory devices.

The magnitude of the “set” current is particularly important for bipolarswitching applications that require the current steering element 216 tobe reverse biased to “set” the resistance of the memory element into alow resistance state. In this case, the act of driving a high currentthrough the current steering device 216, in a non-forward direction, canbreakdown, generate heat within and ultimately damage the materiallayers used to form the current steering element 216 and memory element112, which will reduce the current steering element's and/or memoryelement's effective lifetime.

Because the current steering device 216 provides the primary voltagedrop in the standard switching memory device 200A during the “set”operation (e.g., switch to “on” state), the current steering device 216often is required to operate near its breakdown voltage to reliablycause the variable resistance layer 206 to switch. The application ofthe current steering device 216 in this regime will cause its impedanceto drop over time due to damage to the materials in the formed layer.Typically the resistance (R_(CSD)) of an undamaged reverse biased diodetype current steering device, for example, may be in a range betweenabout 1 and about 100 mega-ohms (MΩ), whereas the resistance of aforward biased diode type current steering device may be between about 1and about 20 kilo-ohms (kΩ).

Therefore, after performing the “set” operation by applying the “set”switching pulse 411, it is common to apply a “sensing” pulse 412 toassure that the logic “one” state has been achieved. The application ofa sensing pulse 412, such as sensing pulse 404 in FIG. 4B, is generallyperformed by applying a V_(READ) voltage (e.g., +0.5V) across theelectrodes 102, 118.

If the “set” operation was performed correctly, the current through astandard switching memory device 200A during this sensing step willequal the I_(ON) current, which equals the V_(READ) voltage divided bythe impedance of the circuit. For a standard switching memory device200A that has a variable resistance layer 206 that is in a lowresistance state, the I_(ON) current will approximately equal to theV_(READ) voltage divided by the impedance of the current steering device(e.g., I_(ON)=˜V_(READ)/R_(CSD)).

Next, in cases where it desirable to change the memory element 112 froma low resistance state (i.e., logic “one” state) to a high resistancestate (i.e., logic “zero” state) a “reset” switching pulse 413, such asreset switching pulse 405, is delivered through the standard switchingmemory device 200A. The largest current that is delivered through theswitching memory device during the “reset” operation will be achievedwhen the initial “reset” current I_(C) flows through the device.

The current flowing through the device during the “reset” operation willthen tend to drop as the variable resistance layer 206 switches from aLRS to a HRS. Therefore, the pulse 413, which is schematicallyillustrated in FIG. 4B, may have a high current portion 419 at the startof the delivered pulse 413 and a stable region that equals the “reset”current I₄ during the later stages of the “reset” operation. Thus, the“reset” current I₄ achieved during the “reset” switching pulse 413 willgenerally equal the final “reset” current I_(D) and the maximum currentachieved during the pulse 413 will equal the initial “reset” currentI_(C).

The magnitude of the current required to switch the memory element 112to a high resistance state from a low resistance state depends on themagnitude of the current used to “set” the device in the low resistancestate. If a high “set” current, such as current I₁, is delivered to thememory element 112, then a higher “reset” current is required to achievea desirable high resistance state.

Stated another way, the difference between the initial “reset” currentI_(C), and/or the final “reset” current I_(D), and the minimum “reset”current I_(MRC) current needs to be larger than necessary to cause thedevice to switch from the “on” to the “off” state if the magnitude ofthe prior applied “set” current is too far from the minimum “set”current I_(MSC). The larger than necessary swings in the current used toswitch between the “on” and “off” states can damage the materials andcomponents in the switching memory device, thus affecting the memoryelement's lifetime and reliability.

Next, after delivering the “reset” switching pulse 413 it is common toapply a “sensing” pulse 412, such as sensing pulse 406 in FIG. 4B, toassure that the logic “zero” state has been achieved. The sensing pulse412 is generally performed by applying a V_(READ) voltage (e.g., +0.5V)across the electrodes 102, 118. If a “reset” operation was performedcorrectly, the current through a standard switching memory device 200Aduring this sensing step will equal the I_(OFF) current, which for thestandard switching memory device 200A will equal to the V_(READ) voltagedivided by the sum of the current steering device impedance resistance(R_(CSD)) and the resistance of the variable layer (R_(VR)). Therefore,in one example, the I_(OFF) current for the standard memory device 200Awill be as follows:I_(OFF) =˜V _(READ)/(R _(CSD) +R _(VR))

FIG. 5A is a schematic side cross-sectional view of some embodiments ofan improved switching memory device 200B that contains a memory element112 and a current steering device 216 that are disposed betweenelectrodes 102 and 118 and are formed over a portion of a substrate 201.The switching memory device 200B contains a current limiting component,such as current limiting layer 204 that is configured to improve thedevice's switching performance and lifetime. In this configuration, thememory element 112 will generally contain a top electrode 102, a currentlimiting layer 204, a variable resistance layer 206 and an optionalintermediate electrode 210, or additional conductive layer.

In some embodiments, the current limiting layer 204 is disposed withinthe improved switching memory device 200B close to the variableresistance layer 206 and/or current steering device 216 to effectivelylimit or prevent the propagating programming current pulses (e.g., “set”or “reset” pulses) delivered through the switching memory device 200Bfrom damaging the layers formed therein during normal device operation.Positioning the current limiting layer 204 near the variable resistancelayer 206 and/or current steering device 216 can be important inswitching memory devices 200B that utilize high speed transientprogramming pulses, such as square or trapezoidal shaped pulses that areless than about 1 ms in length.

It is believed that the use of an externally positioned resistiveelement in a circuit in which the switching memory device 200B isformed, such as resistive layers or structures formed on other parts ofthe chip in which the switching memory device 200B is formed, will noteffectively prevent the delivered high speed programming pulse energyfrom causing the materials in the variable resistance layer 206 and/orcurrent steering device 216 from breaking down when the high speedtransient programming pulses are delivered through the switching memorydevice 200B.

It is believed that the propagation delay created by the transmission ofthe high speed programming pulse through the length of the electricalcircuit formed between the external resistive element and the switchingmemory device 200B components (e.g., variable resistance layer 206 andcurrent steering device 216) will generally prevent the externallypositioned resistive element from effectively reducing or dropping theinstantaneous amount of energy passing through the variable resistancelayer 206 and current steering device 216 as the high speed programmingpulse passes through the switching memory device 200B in the forwardand/or reverse bias directions.

In some embodiments, the current limiting layer 204 is disposed in closeproximity to the variable resistance layer 206, such as substantiallyadjacent to the variable resistance layer 206 with a separation layer205 between the current limiting layer 204 and the variable resistancelayer 206. The position of the current limiting layer 204 in theswitching memory devices 200B need not be limited to the position shownin FIG. 5A, and thus the configuration as shown is not intended to belimiting as to the scope of the invention described herein.

In some embodiments, the current limiting layer 204 is disposed betweenthe variable resistance layer 206 and the current steering device 216.In some embodiments, the current limiting layer 204 can be placedbetween any adjacently positioned layers in the formed switching memorydevice 200B, such between the intermediate electrode 210 and thevariable resistance layer 206 or between the intermediate electrode 210and the current steering layer 216.

In some embodiments, as illustrated in FIG. 5A, the electrodes 102 and118 may each comprise more than one layer of conductive material. In oneconfiguration, the top electrode 102 may comprise a first conductivelayer 102A and a second conductive layer 1028, and the bottom electrode118 may comprise a first conductive layer 118A and a second conductivelayer 1188. In this case, the first conductive layer 102A in the topelectrode 102 and the first conductive layer 118A in the bottomelectrode 118 can be used to interconnect multiple switching memorydevices 200B in an array of formed devices, and thus may act asword-lines or bit-lines.

The second conductive layer 102B and the second conductive layer 1188may each comprise a material that has desirable electrical properties(e.g., work function) so that these layers can help improve theelectrical characteristics of the memory element 200B. The firstconductive layer 102A and/or first conductive layer 118A may comprise,for example, tungsten (W), aluminum (Al) or copper (Cu), whereas thesecond conductive layer 102B and/or the second conductive layer 118B maycomprise, for example, titanium (Ti), titanium nitride (TiN), or dopedpoly-silicon.

The configuration shown in FIG. 5A and discussed herein is not intendedto limit the scope of the invention described herein, because, forexample, the electrodes 102 and 118 may comprise a single conductivelayer, and the position of the various layers, or number of layers, inthe stack of layers used to form switching memory device may be alteredwithout deviating from the basic scope of the invention describedherein.

FIG. 5B is a schematic side cross-sectional view of another embodimentof an improved switching memory device 200B as previously shown in FIG.5A with additional and optional stabilizing layers 207 and 208 disposedon both sides of the current limiting layer 204 and between theseparation layer 205 and the top electrode 102. The stabilizing layersmay comprise a conductive oxide for example indium tin oxide (ITO) oriridium oxide (IrOx), or Indium Zinc Oxide (IZO).

FIG. 5C schematically illustrates an electrical circuit formed by theswitching memory device 200B shown in FIG. 5A. As illustrated in FIG.5C, the electrical circuit within the switching memory device 200Bincludes a top electrode impedance (i.e., resistance R_(TEL)) created bythe top electrode 102 layer(s), a current limiting layer impedance(i.e., resistance R_(CLL)) created by the current limiting layer 204, avariable resistance layer impedance (i.e., resistance R_(VR)) created bythe variable resistance layer 206, an intermediate electrode impedance(i.e., resistance R_(IEL)) created by the intermediate electrode 210layer(s), a current steering device impedance (i.e., resistance R_(CSD))created by the current steering device 206 and a bottom electrodeimpedance (i.e., resistance R_(BEL)) created by the bottom electrode 118layer(s).

Referring back to FIG. 4B, in one example, a “set” switching pulse 411,or set pulse 403, is delivered through the switching memory device 200Bto create a low resistance state, or logic “one” state. In thisconfiguration, a “set” voltage V_(SET) is applied across electrodes 102and 118, which creates a set current I₃ to flow through the switchingmemory device 200B, due to the impedance of the components in theswitching memory device 200B.

The set current I₃ will equal the V_(SET) voltage divided by the sum ofthe impedances in the switching memory device 200B. Therefore, in oneexample, the set current I₃ will equal the following:I ₃ =V _(SET)/(R _(TEL) +R _(CLL) +R _(VR) +R _(IEL) +R _(CSD) +R_(BEL)).Therefore, because the impedance of the electrodes is generally small,due to the need to reduce the power loss in the device, and theimpedance of the variable resistance layer is desirably low to achieve alogic “one” state, the impedance of the current steering device and thecurrent limiting layer will dominate the circuit (e.g.,(R_(CLL)+R_(CSD*))>>R_(TEL)+R_(IEL)+R_(BEL)+R_(VR)) and the impedance ofthe circuit in this state is effectively equal to the sum of theimpedances of the current steering device and the current limiting layer(i.e., R_(CLL)+R_(CSD)).

Therefore, referring to FIG. 4B, the magnitude of the set current I₃created by a “set” pulse 403 will equal a current (I₃), which can beadjusted by the selection of a desired fixed impedance value of thecurrent limiting layer 204. Due to the presence of the added impedance(R_(CLL)) of the current limiting layer 204 in the switching memorydevice 200B, versus the standard switching memory device 200A (FIG. 3A),the actual impedance (R_(CSD*)) of the current steering device 216 willgenerally be greater than the impedance of a current steering device 216disposed in the standard current steering device 200A, because the addedvoltage drop of the current limiting layer 204 in the device circuitwill prevent the current steering device 216 from being damaged by theapplication of the programming currents during normal operation.

As noted above, because the current steering device 216 in a standardswitching memory device 200A (FIG. 3A) is the primary voltage dropduring the “set” operation (e.g., switch to “on” state), the currentsteering device 216 often is required to operate near its breakdownvoltage to reliably cause the variable resistance layer 206 to switch,which will generally not be the case in the switching memory device 200Bdue to the added voltage drop provided by the current limiting layer204.

The addition of the current limiting layer 204 in the switching memorydevice 200B reduces the voltage applied across the current steeringdevice 216, and thus prevents the impedance of the current steeringdevice 216 from dropping due to the application of a voltage near thebreakdown state of the material and/or degrading over time due to damagecreated by the repetitive application of the programming voltages.

Referring to FIG. 4B, in general, it is desirable to form the currentlimiting layer 204 so that its impedance (R_(CLL)) limits the currentthrough the memory element 112 to a value (e.g., current I₂) that isjust greater than the minimum “set” current I_(MSC), as illustrated bypulse 402, and still allow the “on” logic state to be reliably “set” bythe applied V_(SET) voltage.

It is believed that by adding the current limiting layer 204 to a memoryelement 112 can also help reduce the apparent minimum I_(MSC) currentrequired to cause the variable resistance layer 206 to change to a lowresistive state, because the addition of the current limiting layerimpedance (R_(CLL)) in the circuit will reduce the swing in currentbetween the “set” and “reset” switching currents at the same fixedapplied voltage, thus affecting the density and movement of the traps inthe variable resistance layer 206.

Not intending to be bound by theory, it is believed that when a smaller“on” state switching current is applied to a device that the formedfilament(s), or aligned traps, in the variable resistance layer will besmaller in size than if a higher “on” current is applied, thus makingthe filament(s) easier to alter during the “reset” phase of theresistive switching process.

In some embodiments, it is desirable to form the current limiting layer204 from a material that will not significantly vary in resistance whenthe “set” and “reset” switching currents are applied to the switchingmemory device 200B. Forming the current limiting layer 204 from amaterial that has a generally constant resistance will assure that theswitching characteristics of the device will not change over the life ofthe switching memory device 200B, due to changes in the material in theformed layer.

Also, forming the current limiting layer 204 from a material that doesnot vary in resistance during the programming steps, due to the use of anon-resistive switching material, has many advantages that include: 1)less variability in the electrical properties of the formed layer due tovariations in the deposition process (e.g., defect density variations);2) less variability in the electrical properties of the formed layerover the lifetime of the formed memory device due to any physical orchemical change in the current limiting layer material; and 3) a lowerdevice performance variability that is created by differences in the“forming” process (i.e., application of the forming voltage (V_(FORM))).It is desirable to form the current limiting layer 204 so that itsmaterial and electrical properties will not degrade or breakdown duringthe “forming” process, and also during normal repetitive operation ofthe switching memory device 200B.

Device Structure and Formation Processes

In one embodiment, as discussed above, a memory array 100 (FIG. 1)comprises a plurality of switching memory devices 200B that are eachinterconnected by the electrodes 102 and 108. As illustrated in FIG. 5A,a switching memory device 200B may comprise a top electrode 102, acurrent limiting layer 204, a separation layer 205, a variableresistance layer 206, an intermediate electrode 210, a current steeringdevice 216 and an electrode 118. In one configuration, as noted above,the current steering device 216 comprises a p-n junction diode, p-i-ndiode, transistor, or other similar device that is disposed betweenelectrode 102 and memory element 112, or between the electrode 118 andmemory element 112.

In one example, the current steering device 216 may include two or morelayers of a semiconductor material, such as two or more doped siliconlayers, that are configured to direct the flow of current through thedevice. In one example, the current steering device is a diode thatcomprises a p-doped silicon layer (not shown), an un-doped intrinsiclayer (not shown), and an n-doped silicon layer (not shown) that has anoverall resistance between about 1 kΩ and about 100 MΩ. The overallresistance will generally depend on the type of current steering devicethat is formed and in what direction current is flowing through thedevice (e.g., forward or reversed biased)

The electrodes 102, 210 and 118 disposed in the switching memory device200B are generally formed from a conductive material that has adesirable conductivity and work function. In some configurations, theelectrode 102, 210 and/or 118 disposed in the switching memory device200B are each formed from different materials, which may include, butare not limited to p-type polysilicon, n-type polysilicon, transitionmetals, transition metal alloys, transition metal nitrides, andtransition metal carbides.

In one example, the electrode 102 and the electrode 118 comprise ametal, metal alloy, metal nitride or metal carbide formed from anelement selected from a group consisting of titanium (Ti), tungsten (W),tantalum (Ta), cobalt (Co), molybdenum (Mo), nickel (Ni), vanadium (V),hafnium (Hf) aluminum (Al), copper (Cu), platinum (Pt), palladium (Pd),iridium (Ir), ruthenium (Ru), and combination thereof. In one example,the electrodes 102 and 118 comprise a metal alloy selected from thegroup of a titanium/aluminum alloy, or a silicon-doped aluminum (AlSi).

In some embodiments of the switching memory devices 200B, the electrodes102 and 118 comprise a metal, such as a transition metal, transitionmetal alloy, transition metal carbide, transition metal nitride (e.g.,TiN), non-mobile metal such as gold (Au) or platinum (Pt), and theintermediate electrode 210 comprises a heavily doped semiconductormaterial, such as a heavily doped silicon material (e.g., n-typepolysilicon material) that interfaces well with the current steeringdevice 216. In one example, the intermediate electrode 210 comprisespolysilicon and is between about 50 Å and about 500 Å thick, and theelectrodes 102 and 118 are between about 50 Å and 5000 Å thick andcomprise a metal, such as titanium nitride (TiN).

The variable resistance layer 206 disposed in a switching memory device200B can be a dielectric material, such as a metal oxide material orother similar material that can be switched between at least two or morestable resistive states. In some embodiments, the variable resistancelayer 206 is a high bandgap material (e.g., bandgap >4 electron volts(eVs)), such as hafnium oxide (Hf_(x)O_(y)), tantalum oxide(Ta_(x)O_(y)), aluminum oxide (Al_(x)O_(y)), lanthanum oxide(La_(x)O_(y)), yttrium oxide (Y_(x)O_(y)), dysprosium oxide(Dy_(x)O_(y)), ytterbium oxide (Yb_(x)O_(y)) and zirconium oxide(Zr_(x)O_(y)).

Using high band gap variable resistance layer materials improves dataretention in the memory element 112, and reduces the leakage current inthe formed memory element device, because the amount of trapped chargein the variable resistance layer material will be less than a lower bandgap material, and the high band gap materials create a large barrierheight that the carriers have to cross during the read, set and resetoperations. In other embodiments, lower bandgap metal oxide materialscan be used, such as titanium oxide (TiO_(x)), nickel oxide (NiO)_(x) orcerium oxide (CeO_(x)) may be advantageous for some embodiments.

In some cases, a semiconductive metal oxide (p-type or n-type) such aszinc oxides (Zn_(x)O_(y)), copper oxides (Cu_(x)O_(y)), and theirnonstoichiometric and doped variants can be used. The variableresistance layer 206 may comprise a metal oxide (e.g., HfO₂) layerformed to a thickness of between about 10 Å and about 100 Å. In oneconfiguration, the variable resistance layer 206 is doped with amaterial that has an affinity for oxygen (e.g., transition metals (Al,Ti, Zr)) to form a metal-rich variable resistance layer (e.g., HfO_(1.7)vs. HfO₂), which is deficient in oxygen, and thus has a larger number ofoxygen vacancy type defects.

The additional vacancy defects can reduce the required switching andforming voltages, reduce the device operating current(s), and reduce thedevice to device variation in a formed memory element. In one example,the variable resistance layer 206 may comprise a metal oxide layer, suchas Hf_(x)O_(y), Ta_(x)O_(y), Al_(x)O_(y), La_(x)O_(y), Y_(x)O_(y),Dy_(x)O_(y), Yb_(x)O_(y) and/or Zr_(x)O_(y), formed to a thickness ofbetween about 20 Å and about 100 Å, such as between about 30 Å and about50 Å. The variable resistance layer 206 can be deposited using anydesired technique, but in some embodiments described herein is depositedusing an ALD process.

In other embodiments, the variable resistance layer 206 can be depositedusing a CVD (e.g., LPCVD, PECVD) or ALD (e.g., PEALD), physical vapordeposition (PVD), liquid deposition processes, and epitaxy processes. Itis believed that PEALD processes can be used to control defects andimprove switching and forming voltages in some embodiments. In oneexample, an ALD process using tetrakis(dimethylamino)hafnium (TDMAH) andan oxygen containing precursor at a temperature of about 250° C. is usedto form an 50 Å thick hafnium oxide (Hf_(x)O_(y)) containing variableresistance layer 206.

In some embodiments, the current limiting layer 204 comprises a varistorthat can be reliably and consistently formed within the switching memorydevices 200B. In one configuration of the memory element 112, the formedvaristor type current limiting layer 204 creates a barrier that is usedto adjust the ease with which current will flow through the formeddevice when a voltage is applied across the electrodes.

The added barrier to current flow will tend to reduce the magnitude ofthe I_(ON) and I_(OFF) current that flow through the device duringoperation, due to the increased energy required to move the electronsthrough the varistor layer. A varistor layer comprises a dielectriclayer that effectively has a nonlinear current versus voltage (I-V)curve, due to its low electrical conductivity at low values of electricfield. At higher field values, individual grains of the varistormaterial break down and start conducting current along their boundaries,leading to current flow.

To achieve a current limiting layer that has desirable electrical and/orphysical properties, one or more steps in a current limiting layer 204deposition process can be adjusted to form a varistor layer that hasdesirable properties. As discussed above, in some cases it is desirableto adjust the resistance of the current limiting layer 204, so that itmatches the resistance of the formed current steering device 216 in theformed switching memory device 200B. One skilled in the art willappreciate that the resistance (R) to current flow through the varistorlayer can be adjusted by varying the thickness, material composition(i.e., doping levels), grain size, or crystalline structure.

Because the cross-sectional area (A) of the device is generally fixed bythe size and lateral spacing of the switching memory devices 200B, andthus is generally not easily varied from one switching memory device tothe next, the resistance R of the current limiting layer 204 can becontrolled by the adjustment of the thickness “t” (FIGS. 5A, 5B) and thegrain size ‘d.’ Typical deposition processes may include ALD, PVD andCVD processes that can be tailored to adjust the electrical propertiesand thickness of the deposited current limiting layer 204.

In one example, for a memory element 112 that is about 150 nm×150 nm insize, a current limiting layer 204 that is about 50 Å thick, and has anequivalent resistivity of 500Ω-cm will achieve a resistance of about 1MΩ, to match the resistance found in a current steering device that hasa resistance of about 1 MΩ. In another example, the current limitinglayer 204 is formed so that its impedance (R_(CLL)) is between about 10kΩ and about 10 MΩ, such as between about 100 kΩ and about 1 MΩ.

The specific thickness would be determined from its process-dependentgrain size and desired operating voltage by the relationship shown inEqn. 1:V _(B) =tv _(g) /d  Eqn. 1

Where V_(B) is the breakdown voltage desired across the varistor (thisshould be between V_(SENSE) and the lower of the magnitude of V_(SET)and V_(RESET)), t is the thickness of the varistor film, d is thevaristor material grain size, and v_(g) is the breakdown voltage perintragranular barrier (typically 3.2 V/grain in thin films). Thisrelationship self-consistently determines the relationship betweenprocess (which decides grain size), design (such as film thickness), andapplication (such as V_(READ), V_(SET), and V_(RESET)).

Materials used to form the varistor type current limiting layer 204include various dielectric materials that generally include variousmetal oxides. In one configuration, the current limiting layer 204includes a varistor that has a breakdown voltage that exceeds thebreakdown voltage of the variable resistance layer 206. Current limitinglayer 204 materials that have a breakdown voltage that is less than thebreakdown voltage of variable resistance layer 206 material will becomedamaged during application of the forming voltage (V_(FORM)), which isdiscussed above.

Therefore, in some embodiments of the invention, the material in aformed current limiting layer 204 disposed in a formed memory element112 has a breakdown voltage that is greater than the breakdown voltageof the material found in the variable resistance layer 206. In oneexample, the current limiting layer 204 comprises a zinc oxide (ZnO_(x))layer doped with bismuth, cobalt, or manganese that is formed using aPVD, CVD or ALD type process. In some configurations, the composition ofthe metal containing layer can be adjusted to change the resistivity ofthe formed layer. In some deposition processes, the resistivity of theformed oxygen containing layer is controlled by adjusting the partialpressure of oxygen in the processing region of the deposition chamberduring a CVD, PVD, or ALD deposition process.

The use of varistor layers as described above, when used in series withthe variable resistance layer 206 acts as a current limiting elementthat will reduce leakage. However, when the varistor layer is formed sothat it is in direct contact with the variable resistance layer 206, theprocess of forming the varistor layer can contaminate the variableresistance layer 206, and thus degrade the performance of the device. Toprevent the formed varistor layer or other subsequent processing fromdamaging the interface or properties of variable resistance layer 206, aseparation layer 205 can be used as a contamination barrier layer andprevent the diffusion of the components used to form the varistor layerinto the variable resistance layer 206.

It is generally desirable to form the current limiting layer 204 so thatits material and electrical properties will not degrade or breakdownduring the often high current “burn-in” type device preparation steps,such as the “electrical forming” process, and also during normalrepetitive operation of the nonvolatile resistive switching memorydevice. However, in some device operation regimes certain varistorlayers may still be susceptible to breakdown during forming and thustend to degrade (e.g., current leakage) during the application of normaloperation currents, and thus causing its resistivity to vary over time.

In some embodiments, by positioning one or more stabilizing layers, 207,208, on either side of the varistor layer, the breakdown of the currentlimiting layer 204 can be reduced. The stabilizing layers generallycomprise indium tin oxide (ITO) and iridium oxide (IrO_(x)) and indiumzinc oxide (IZO). It is believed that the mobile oxygen in thestabilizing layers can be used to replenish the oxygen atoms in thevaristor layer that are undesirably moved during the application offorming a bias during the forming process.

The replenishment of the oxygen atoms to the vacancies formed in thevaristor layer during the forming process can assist in maintaining thestoichiometry of the tunnel oxide material and thus preventing devicedegradation during the forming process. Furthermore, thermalconsiderations during the normal switching operation can createadditional oxygen vacancies in the current limiting layer 204 while thepresence of the stabilizing layers can offset this effect, bymaintaining the electrical properties of the varistor layer material,and extending the operational life of the nonvolatile resistiveswitching memory device.

Switching Memory Device Fabrication Processes

FIG. 6 illustrates a process sequence 600 that can be used to form amemory element 112 components in a switching memory device 200Billustrated in FIGS. 5A & 5B, according to embodiments of the invention.Although omitted from the discussion below, the electrode 118 andcurrent steering device 216 elements can be formed over a portion of asubstrate 201, such as a silicon substrate, by use of a physical vapordeposition (PVD), chemical vapor deposition (CVD), atomic layerdeposition (ALD), or other similar process that is well known in theart.

In some configurations, it is desirable to determine the empirical ortheoretical resistance of the current steering device 216 structure inthe memory element 112, so that the resistance of the current limitinglayer 204 can be adjusted relative to the expected resistance of theformed current steering device 216. In one example, the current steeringdevice 216 is a diode that comprises a p-doped silicon layer (not shown)that is formed by a CVD process, an un-doped intrinsic layer (not shown)that is formed by an CVD process, and an n-doped silicon layer (notshown) that is formed by a CVD process. In one example, the electrode118 comprises a layer of titanium nitride (TiN) that is between about500 Å and 1 μm thick and is formed by use of a PVD process.

Referring to FIGS. 5A and 6, at step 601 an intermediate electrode 210is formed over a substrate 201. In one embodiment, the intermediateelectrode 210 is a highly doped polysilicon layer that is formed using aconventional CVD or ALD type polysilicon deposition technique. In somecases, an optional native oxide layer removal step may be performedafter forming the intermediate electrode layer 210 by use of a wetchemical processing technique, or conventional dry clean process that isperformed in a plasma processing chamber. In one example, theintermediate electrode 210 comprises polysilicon that is between about50 Å and about 5000 Å thick, which is formed by use of a CVD or ALDpolysilicon deposition process.

Referring to FIGS. 5A and 6, at step 602, the variable resistance layer206 is deposited over the intermediate electrode 210 using a PVD, CVD orALD deposition process. The variable resistance layer 206 may comprise ametal oxide layer, such as Hf_(x)O_(y), Ta_(x)O_(y), Al_(x)O_(y),La_(x)O_(y), Y_(x)O_(y), Dy_(x)O_(y), Yb_(x)O_(y) and/or Zr_(x)O_(y),formed to a thickness of between about 20 Å and about 100 Å, such asbetween about 30 Å and about 50 Å.

The variable resistance layer 206 can be deposited using any desiredtechnique, but in some embodiments described herein is deposited usingan ALD process. In one example, an ALD process usingtetrakis(dimethylamino)hafnium (TDMAH) and an oxygen containingprecursor (e.g., water vapor) at a temperature of about 250° C. is usedto form a 30 Å thick hafnium oxide (Hf_(x)O_(y)) which acts as thevariable resistance layer 206.

At step 603, as depicted in FIGS. 5A and 6, a separation layer 205 isformed over the variable resistance layer 206 as shown in FIG. 5A. Inone example, the separation layer 205 may comprise titanium nitride(TiN) or tantalum nitride (TaN). The separation layer 205 may bedeposited using a deposition process, such as PVD, CVD, ALD or othersimilar process. In one example, the separation layer 205 is betweenabout 30 Å and 100 Å thick. In one example, a PVD process is used toform a separation layer 205 that comprises titanium nitride (TiN) thatis between about 30 Å and 1000 Å thick.

Optionally at step 604, as depicted in FIGS. 5B and 6, a stabilizinglayer 208 may be formed over the separation layer 205. In one example,the stabilizing layer 208 may comprise indium tin oxide (ITO) or iridiumoxide (IrO₂). The stabilizing layer 208 may be deposited using adeposition process, such as a PVD, CVD, ALD or other similar process. Inone example, the stabilizing layer 208 is greater than or equal to 50 Åthick. In one example, the thickness range of the stabilizing layer 208is between about 30 Å and 100 Å. In one example, a PVD process is usedto form a stabilizing layer 208 that comprises indium tin oxide (ITO)and is between about 30 Å and 100 Å thick.

At step 605, as depicted in FIGS. 5A and 6, a current limiting layer 204is formed using a deposition process, such as a PVD, CVD, ALD or othersimilar process. In some embodiments, the current limiting layer 204 isa varistor layer (e.g., doped ZnO_(x)), that is formed by use of a PVD,CVD or ALD process. In one example, the current limiting layer 204 maybe formed to a thickness between about 50 Å and about 60 Å, and comprisea material such as ZnO_(x) doped with at least one of bismuth, cobalt,or manganese.

In one example, the current limiting layer 204 layer is formed using aPVD process that deposits an doped ZnO_(x) layer at a deposition rate ofbetween about 0.1 to 1 Å/minute using a zinc target and maintaining theprocessing environment during the PVD deposition process to betweenabout 10 and about 50% oxygen (O₂) and the balance being argon (Ar) gas.The dopants can be incorporated into the target or may be co-sputteredfrom a separate target.

Maintaining the oxygen concentration in a PVD processing environment toa concentration of greater than about 10% will form a dielectric layer.Therefore, one can adjust the layer thickness and resistivity to form azinc oxide layer containing current limiting layer 204 that has adesirable resistance. In one process example, the oxygen concentrationin the processing environment during deposition is controlled to form azinc oxide (ZnO_(x)) layer that has a desirable thin-film resistivitywithin a range of 100-10,000 Ohm-cm.

Optionally at step 606, as depicted in FIGS. 5B and 6, a stabilizinglayer 207 may be formed over the current limiting layer 204 comprisingindium tin oxide (ITO) or iridium oxide (IrO₂) or IZO. The stabilizinglayer 207 may be deposited using a deposition process, such as a PVD,CVD, ALD or other similar process. In one example, the stabilizing layer207 has a thickness greater than or equal to 50 Å. In one example, athickness range between about 30 Å and 1000 Å. In one example, a PVDprocess is used to form a stabilizing layer 208 that comprises indiumtin oxide (ITO) and is between about 30 Å and 1000 Å thick.

At step 607, the electrode 102 is formed over the current limiting layer204 as shown in FIG. 5A or optionally over the stabilizing layer asshown in FIG. 5B, using one or more of the materials that are discussedabove. The electrode layer 102 may be deposited using a depositionprocess, such as a PVD, CVD, ALD or other similar process. In oneexample, the electrode layer 102 is between about 100 Å and 1000 Åthick. In one example, a PVD process is used to form an electrode layer102 that comprises titanium nitride (TiN) and is between about 100 Å and1000 Å thick.

At step 608, the formed switching memory device 200B is optionallyannealed at a temperature of greater than about 450° C. In one example,the formed switching memory device 200B is annealed at a temperature ofgreater than about 700° C. In another example, the formed switchingmemory device 200B is annealed at a temperature of between about 450° C.and about 1000° C. for a period of time between about 30 seconds andabout 20 minutes. The process(es) performed at step 708, are generallyconfigured to cause the layers disposed in the switching memory device200B to form a desirable interface between adjacent layers as well asactivate and/or desirably process the other layers formed in theswitching memory device.

Process and Device Examples

In one example of a process of forming a switching memory device (FIG.5C), after performing the steps 601-608 in the processing sequence 600,a memory element 112 is formed that comprises: an intermediate electrode210 comprising an n-doped polysilicon layer, a variable resistance layer206 that is about 50 Å thick and comprises hafnium oxide (HfO_(x)), aseparation layer 205 that is between 30 Å and 1000 Å thick and comprisestantalum nitride (TaN), a current limiting layer 204 that is betweenabout 50 Å and 500 Å thick and comprises doped zinc oxide (ZnO_(x)), andan electrode 102 that comprises a layer of titanium nitride (TiN). Afterforming the switching memory device 200B (FIG. 5A), then at least onethermal processing step is performed, such as step 608.

In another example of a process of forming a switching memory device,after performing the steps 601-608, a memory element 112 is formed thatcomprises: an intermediate electrode 210 comprising an n-dopedpolysilicon layer, a variable resistance layer 206 that is about 50 Athick and comprises hafnium oxide (HfO_(x)), a separation layer 205 thatis between 30 Å and 1000 Å thick and comprises tantalum nitride (TaN), astabilizing layer 208 that is between 30 Å and 500 Å and comprisesindium tin oxide (ITO), a current limiting layer 204 that is betweenabout 50 Å and 500 Å thick and comprises doped zinc oxide (ZnO_(x)), astabilizing layer 207 that is between 30 Å and 500 Å and comprisesindium tin oxide (ITO) and an electrode 102 that comprises a layer oftitanium nitride (TiN). After forming the switching memory device 200B,then at least one thermal processing step is performed, such as step608.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the artwithout departing from the scope and spirit of the invention as definedby the claims that follow.

The invention claimed is:
 1. A nonvolatile memory element, comprising: afirst electrode; a second electrode; a variable resistance layerdisposed between the first electrode and the second electrode, thevariable resistance layer comprising a metal oxide; a current limitinglayer disposed between the variable resistance layer and the firstelectrode, wherein the current limiting layer comprises a varistorlayer; and an oxygen deficient material layer disposed between thecurrent limiting layer and the variable resistance layer, wherein: thecurrent limiting layer is disposed between a first material layer and asecond material layer, and each of the first material layer and thesecond material layer comprise a material selected from the group ofindium tin oxide and iridium oxide, and wherein the materials selectedfor each first material layer and second material layer are not thesame.
 2. The nonvolatile memory element of claim 1, wherein the variableresistance layer comprises a material selected from the group of hafniumoxide, zirconium oxide, lanthanum oxide, and aluminum oxide.
 3. Thenonvolatile memory element of claim 1, wherein the variable resistancelayer has a thickness of between 20 angstroms and 100 angstroms.
 4. Thenonvolatile memory element of claim 1, wherein the current limitinglayer comprises a material comprised of zinc oxide doped with one ormore of bismuth, cobalt, or manganese.
 5. The nonvolatile memory elementof claim 1, wherein the current limiting layer has a thickness ofbetween 50 angstroms and 500 angstroms.
 6. The nonvolatile memoryelement of claim 1, wherein the oxygen deficient material layercomprises a material selected from the group of tantalum nitride,titanium nitride and tungsten nitride, silicon oxy-nitride, aluminumoxy-nitride, aluminum nitride, hafnium nitride zirconium nitride, boronnitride, calcium nitride, ruthenium titanium nitride, gold, zirconiumplatinum and platinum beryllium.
 7. The nonvolatile memory element ofclaim 1, wherein the current limiting layer has a thickness of between50 angstroms and 100 angstroms.
 8. A nonvolatile memory element,comprising: a first electrode; a second electrode; a variable resistancelayer disposed between the first electrode and the second electrode, thevariable resistance layer comprising a metal oxide; a current limitinglayer disposed between the first electrode and the variable resistancelayer, the current limiting layer comprising a varistor layer; an oxygendeficient material layer disposed between the current limiting layer andthe variable resistance layer, the oxygen deficient material layeroperable to inhibit oxygen from the variable resistance layer; a firststabilizing layer; and a second stabilizing layer, wherein: the currentlimiting layer is disposed between the first stabilizing layer and thesecond stabilizing layer, and the first stabilizing layer and secondstabilizing layer are operable to provide oxygen to the current limitinglayer, and each of the first stabilizing layer and the secondstabilizing layer comprise a material selected from the group of indiumtin oxide and iridium oxide, and wherein the materials selected for eachfirst stabilizing layer and second stabilizing layer are not the same.9. The nonvolatile memory element of claim 8, wherein the variableresistance layer comprises a material selected from the group of hafniumoxide, zirconium oxide, lanthanum oxide and aluminum oxide.
 10. Thenonvolatile memory element of claim 8, wherein the variable resistancelayer has a thickness of between 20 angstroms and 100 angstroms.
 11. Thenonvolatile memory element of claim 8, wherein the current limitinglayer comprises a material comprised of zinc oxide doped with one ormore of bismuth, cobalt, or manganese.
 12. The nonvolatile memoryelement of claim 8, wherein the current limiting layer has a thicknessof between 50 angstroms and 500 angstroms.
 13. The nonvolatile memoryelement of claim 8, wherein the oxygen deficient material layercomprises a material selected from the group of tantalum nitride,titanium nitride, tungsten nitride, silicon oxy nitride, aluminumoxy-nitride, aluminum nitride, hafnium nitride zirconium nitride, gold,zirconium, platinum and platinum beryllium.
 14. The nonvolatile memoryelement of claim 8, wherein the oxygen deficient material layer has athickness of between 30 angstroms and 1000 angstroms.
 15. Thenonvolatile memory element of claim 8, wherein the first stabilizinglayer and second stabilizing layer each have a thickness of between 50angstroms and 1000 angstroms.
 16. A method of forming a nonvolatilememory element, comprising: forming a first electrode over a substrate;forming a second electrode over the substrate; forming a variableresistance layer between the first electrode and the second electrode,the variable resistance layer comprising a metal oxide; forming acurrent limiting layer between the first electrode and the variableresistance layer; forming a separation layer between the currentlimiting layer and the variable resistance layer, the separation layercomprising an oxygen deficient material; and forming the currentlimiting layer between a fist material layer and a second materiallayer, wherein each of the first material layer and the second materiallayer comprise a material selected from the group of indium tin oxideand iridium oxide, and wherein the materials selected for each firstmaterial layer and second material layer are not the same.
 17. Themethod of claim 16, wherein the separation layer comprises a materialselected from the group of tantalum nitride, titanium nitride andtungsten nitride, silicon oxy-nitride, aluminum oxy-nitride, aluminumnitride, hafnium nitride zirconium nitride, gold, zirconium platinum andplatinum beryllium.
 18. The method of claim 16, wherein the currentlimiting layer comprises a material comprised of zinc oxide doped withone or more of bismuth, cobalt, or manganese.